Friday, December 27, 2013

3D Semiconductors-TSV w/ DRAM Memory

 Four High Bandwidth Memory stacks on one integrated chip.

Hynix just announced System in Package (SIP) on a single circuit board by combining 4 stacked DRAM using Through-Silicon Via (TSV) with AMD graphic chip (see below).

Hynix is trying to advance 3D manufacturing using TSV. TSV is essentially advanced packaging manufacturing where holes are drilled through each chip to connect them electrically when they are stacked on top of each other.

More about Through-Silicon Via (TSV) Introduction - 3D Integration & Through Silicon Via(TSV) and The future of computers: 3D chip stacking

While Samsung announced  in August 3D NAND using 3D during the chip manufacturing 1Tb SSD: 3D Vertical NAND

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Moore’s Law

SK Hynix Develops 4x Faster DRAM

SK Hynix reported on December 26th that it has developed the industry’s first High Bandwidth Memory (HBM) DRAM, using Through-Silicon Via (TSV) chip packaging technology.
TSV is a method of transmitting electrical signals through chips by way of creating an electrode that vertically passes through two or more chips, enhancing performance efficiency and reducing chip size.
The DRAM, which is undergoing review for standardization by the Joint Electron Device Engineering Council (JEDEC), is a high-performance, low-power, high-density memory product.  It only draws 1.2 volts of power per 1GB of data processed per second. Through its 1,024 Input/Output Gateways it can transfer 128GB of data per second, about 4 times faster than GDDR5 with 40% less power required.
SK Hynix used TSV technology to stack 4 DRAM chips on top of each other, each chip only 20nm high. The company worked in conjunction with leading graphic chipset maker AMD to put the chips in a System in Package (SIP) on a single circuit board.
The product is projected to be used in the graphics-heavy high-performance market, with future applications in supercomputer networks and servers.