Thursday, December 13, 2012

Apple iPad 4 – A6X Tear-down

Chipwork's teardown of the new Apple iPad 4 reveals a major redesign of the graphic processor (GPU). The much larger area dedicated to the GPU and wider interface of the DRAM improves the display and touch screen performance of the iPad 4. It probably also helps prolong battery life.

" The A6 is 94mm2 while the A6X is 123mm2 – a full 30% larger.So where did that extra area go? Well, firstly, it did not go to the CPU core. The A6X uses the identical CPU to the A6. Same size, same layout. This is not surprising given that the prior CPU used custom layout techniques, and therefore it would be a huge amount of work to redesign so soon. Much of the extra area has gone to the GPU cores which are up from 3 to 4. More notable is that each of these GPU cores is much larger.On the A6X each GPU core is 8.7mm2 while the A6 GPU cores are only 5.4mm2. The overall area occupied by the A6X GPU cores is more than double that of the A6!

So we see that of the 29 mm2 of new area on the A6X, a full 18.6 mm2 is the result of the increased quantity of graphics processing. Impressive!

Additionally, if you look closely at the GPU cores (which our high magnification scopes allow us to do), we can see they are actually split into sub-cores themselves. Each GPU core is sub-divided into 9 sub-cores (2 sets of 4 identical sub-cores plus a central core). This could be done to allow for more efficient parallel processing, or to allow for a higher maximum clock rate. In either case, these GPUs should result in some blazing graphics on your iPad.

Other items of note:

It looks like the A6X has double the SDRAM interface width of the A6 (again likely to allow for greater graphics processing power).

Other than the CPU, it appears all the other digital cores have new layouts. This chip is not just a minor tweak from the A6, a lot of work has gone into this.

Apple has reduced the number of core PLLs needed from 9 on the A6 to 8 on the A6X. However they have moved them close to the middle of the chip which may allow for better control over clock skew across the chip.

Many of the analog and interface cores have been reused from the A6, however there are also some new interface blocks."

Additional information

Ron Maltiel

Monday, December 3, 2012

3D Flash NAND Devices and Process

The article below discusses developments in 3D Flash NAND. Toshiba and Macronix have different approaches. See more details about Toshiba Next NAND- 3D with 15 Layers.

Applied material discusses processing issues and new equipment to address them.

"According to Applied Materials, building 3D NAND structures in like trying to dig a one-kilometer-deep, three-kilometer-long trench with walls exactly three meters apart, through interleaved rock strata."

Ron Maltiel

3D NAND flash is coming

Brian Bailey - November 15, 2012

Flash memory has very quickly risen from being an obscure memory type to perhaps becoming the dominant memory type for many devices, including music players, cell phones, tablets and now increasingly servers and mainstream PCs. But flash memory does not scale quite as well as the more traditional DRAM that it is replacing. It is thought that DRAM can scale down to 1nm whereas we are already hitting some problems with the scaling of the floating gate in NAND flash. It is not thought that planar NAND can go below 10nm which is only a couple of processes steps away from where we are today.

There are several other types of memory being developed, including spin-torque MRAM and Resistive RAM (ReRAM) that may replace both RAM and flash in the future. Another exciting direction is 3D NAND structures. In some respects this is similar to FinFET development for traditional transistors that are finding their way into 20nm and 14nm processes.

Toshiba is one company pushing 3D NAND processes with its p-BiCS (pipe-shaped Bit Cost Scalable) technology. The thought is that rather than lay the cells flat on the surface, higher densities can be achieved by stacking them on top of each other. This is shown diagrammatically in the figure below. As you can see this is not the same as 3D ICs where multiple substrates are layered on top of each other and connected using through silicon vias (TSV), this is building cells on top of each other to create U shaped bit lines. They currently have 16 layers devices where the hole size is 50nm and Toshiba says that the process becomes cheaper than the traditional NAND processes when more than 15 layers are created. Samples are expected next year and volume shipments by 2015...
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